![]() It has not been published before, and it is not under consideration for publication in any other journals. The manuscript is herewith submitted for publication in the Journal of Telecommunication, Electronic and Computer Engineering (JTEC). Australian Journal of Basic and Applied Sciences, 5(1), pp.55-61. Influence of halo and source/drain implantation on threshold voltage in 45nm pmos device. In Micro and Nanoelectronics (RSM), 2015 IEEE Regional Symposium on (pp. Modeling of 14 nm gate length n-Type MOSFET. International Journal of Integrated Engineering, 7(3).įaizah, Z.N., Ahmad, I., Ker, P.J., Roslan, P.A. Modelling and Characterization of a 14 nm Planar p-Type MOSFET Device. In Semiconductor Electronics (ICSE), 2014 IEEE International Conference on (pp. Statistical process modelling for 32nm high-K/metal gate PMOS device. Maheran, A.A., Faizah, Z.N., Menon, P.S., Ahmad, I., Apte, P.R., Kalaivani, T. International Journal of Electronics, Computer and Communications Technologies, 2(3), pp.27-33. Influence of HALO and source/Drain Implantation Variations on threshold Voltage in 45nm CMOS Technology. Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A., Elgomati, H.A., Majlis, B.Y. Degradation of MOSFETs drive current due to halo ion implantation. A sub-0.1/spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V). Redder, M., Hong, Q.Z., Nandakumar, M., Aur, S., Hu, J.C. Effects of high-K dielectrics with metal gate for electrical characteristics of 18nm NMOS device. In Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on (pp. Cobalt silicide and titanium silicide effects on nano devices. IEEE.Įlgomati, H.A., Majlis, B.Y., Salehuddin, F., Ahmad, I., Zaharim, A. In Semiconductor Electronics (ICSE), 2010 IEEE International Conference on (pp. Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing. Ng, J.A., Sugii, N., Kakushima, K., Ahmet, P., Tsutsui, K., Hattori, T. Selective desorption of interfacial SiO 2. Decomposition of interfacial SiO 2 during HfO 2 deposition. Suppression of subcutaneous oxidation during the deposition of amorphous lanthanum aluminate on silicon. Journal of applied physics, 98(2), p.024314.Įdge, L.F., Schlom, D.G., Brewer, R.T., Chabal, Y.J., Williams, J.R., Chambers, S.A., Hinkle, C., Lucovsky, G., Yang, Y., Stemmer, S. Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction. Lichtenwalner, D.J., Jur, J.S., Kingon, A.I., Agustin, M.P., Yang, Y., Stemmer, S., Goncharova, L.V., Gustafsson, T. MRS Online Proceedings Library Archive, 744. Epitaxial praseodymium oxide: a new high-K dielectric. Materials Science and Engineering: R: Reports, 88, pp.1-41. High-K materials and metal gates for CMOS applications. Conference on Solid State Devices and Materials (Vol. Recent Progress in High-k Dielectric Films for ULSIs. IEEE Transactions on Electron Devices, 46(7), pp.1537-1544. The impact of high-/spl kappa/gate dielectrics and metal gate electrodes on sub- 100 nm MOSFETs. Electronic properties of hafnium oxide: A contribution from defects and traps. ![]() Thin Films on Silicon: Electronic And Photonic Applications, pp.323-367. High-oxides on Si: MOSFET gate dielectrics,”. The finding shows that optimum VTH and ION/IOFF ratio can be achieved by selecting the most suitable halo implant dose in a virtually fabricated 14nm gate-length La2O3-based NMOS device with varying high-k dielectric oxide thickness.Īndo, T., Kwon, U., Krishnan, S., Frank, M.M. In order to achieve the best ION/IOFF ratio for a predetermined range of VTH, halo implant was used to adjust the threshold voltage. A device with high drive current (ION) and low IOFF gives a high on-off current ratio (ION/IOFF), which leads to a faster switching speed for the Ntype Metal Oxide Semiconductor Field Effect Transistor (NMOS). The thickness of high-k gate dielectric influences the threshold voltage (VTH) and off-state leakage current (IOFF). High-k dielectric oxides have been used to replace the widely used silicon dioxide (SiO2) gate dielectrics to overcome physical limits of transistor scaling. High-k dielectric, La2O3, metal gate, NMOS, Abstract Department of Electrical Engineering, Faculty of Engineering, Nilai UniversityĮlectronics Research Group, Institute of Power Engineering, Universiti Tenaga Nasional (UNITEN) ![]()
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